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IRS26310DJPbF
Figure 4: Input/output timing diagram
ITRIP
V IT,TH+
Interval B
Interval C
V IT,TH-
FAULT
RCIN
HOx
t FLT
50%
90%
V RCIN,TH
t FLTCLR
50%
t ITRIP
Figure 5: Detailed view of B & C intervals
Deadtime
This family of HVICs features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs
within IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts
a time period (a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to
ensure that the power switch being turned off has fully turned off before the second power switch is turned on. This
minimum deadtime is automatically inserter whenever the external deadtime is shorter than DT; external deadtimes
larger than DT are not modified by the gate driver. Figure 6 illustrates the deadtime period and the relationship
between the output gate signals.
The deadtime circuitry of the IRS26310D is matched with respect to the high- and low-side outputs of a given
channel; additionally, the deadtimes of each of the three channels are matched. Figure 6 defines the two deadtime
parameters (i.e., DT 1 and DT 2 ) of a specific channel; the deadtime matching parameter (MDT) associated with the
IRS26310D specifies the maximum difference between DT 1 and DT 2 . The MDT parameter also applies when
comparing the DT of one channel of the IRS26310D to that of another.
www.irf.com
17
? 2008 International Rectifier
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